第3周大组讨论会

时间：2018年9月18日，19：00

地点：双子楼B座503

报告人：苏子安

报告题目:A Hybrid DMR latch to tolerate MNU using TDICE and WDICE

报告摘要：With technology scaling, nanoscale CMOS becomes more sensitive to Multiple Node Upsets (MNUs). This paper presents a Multiple Node Upsets Tolerant Hardened Latch based on hybrid Double Modular Redundancy. The proposed latch consists of two elementary cells derived from DICE: one cell is referred to as TDICE cell with four additional NMOS transistors in the feedback lines, the other cell is referred to as WDICE cell with two additional NMOS transistors and two additional PMOS transistors in the feedback lines. Additional transistors in the feedback line of DICE cell improves the resilience to multiple-node upset. Extensive simulation results show the proposed latch can tolerate the DNU with the probability of 100%, and tolerate the TNU with the probability of 95.70%. Also the proposed latch can make a good tradeoff among area, delay, power and robustness.